Datasheet

78K0/Ix2 CHAPTER 11 A/D CONVERTER
R01UH0010EJ0500 Rev.5.00 375
Feb 28, 2012
Figure 11-9. Format of 8-bit A/D conversion result register L for TMXn synchronization (ADCRXnL)
Symbol
ADCRXnL
(n = 0, 1)
Address: FF16H (ADCRX0L), FF18H (ADCRX1L) After reset: 00H R
76543210
Cautions 1. When writing to the A/D converter mode register 0 (ADM0), analog input channel specification
register (ADS), and A/D port configuration registers 0, 1 (ADPC0, ADPC1), the contents of
ADCRXnL may become undefined. Read the conversion result following conversion completion
before writing to ADM0, ADS, ADPC0, and ADPC1. Using timing other than the above may cause
an incorrect conversion result to be read.
2. If data is read from ADCRXnL, a wait cycle is generated. Do not read data from ADCRXnL when
the peripheral hardware clock (f
PRS) is stopped. For details, refer to CHAPTER 31 CAUTIONS
FOR WAIT.
Remark n = 0, 1
(7) Analog input channel specification register (ADS)
ADS specifies the input channel of the analog voltage to be A/D converted and sets the A/D conversion start method.
ADS can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears ADS to 00H.
Remark A/D converter analog input pins differ depending on products.
78K0/IY2: ANI0, ANI1, ANI3 to ANI5
78K0/IA2: ANI0 to ANI5
78K0/IB2: ANI0 to ANI8
Figure 11-10. Format of Analog Input Channel Specification Register (ADS) (1/2)
(1) 78K0/IY2, 78K0/IA2
Address: FF0EH After reset: 00H R/W
Symbol <7> <6> <5> <4> 3 <2> <1> <0>
ADS V12SEL ADOAS ADTRG1 ADTRG0 0 ADS2 ADS1 ADS0
(2) 78K0/IB2
Address: FF0EH After reset: 00H R/W
Symbol <7> <6> <5> <4> <3> <2> <1> <0>
ADS V12SEL ADOAS ADTRG1 ADTRG0 ADS3 ADS2 ADS1 ADS0