Datasheet

78K0/Ix2 CHAPTER 11 A/D CONVERTER
R01UH0010EJ0500 Rev.5.00 374
Feb 28, 2012
(5) 10-bit A/D conversion result register for TMXn synchronization (ADCRXn)
ADCRXn is a 16-bit register that holds the A/D conversion result when A/D conversion is started with the output of 16-
bit timer Xn as the trigger. The higher 6 bits are fixed to 0. Each time A/D conversion ends, the conversion result is
loaded from the successive approximation register.
If A/D conversion is performed with the output of 16-bit timer X0 as the trigger, the higher 2 bits of the conversion
result are stored in FF17H and the lower 8 bits in FF16H of ADCRX0.
If A/D conversion is performed with the output of 16-bit timer X1 as the trigger, the higher 2 bits of the conversion
result are stored in FF19H and the lower 8 bits in FF18H of ADCRX1.
ADCRXn can be read by a 16-bit memory manipulation instruction.
Reset signal generation clears ADCRXn to 0000H.
Figure 11-8. Format of 10-Bit A/D Conversion Result Register for TMXn Synchronization (ADCRXn)
Symbol
Address: FF16H, FF17H (ADCRX0), FF18H, FF19H (ADCRX1) After reset: 0000H R
FF17H (ADCRX0), FF19H (ADCRX1) FF16H (ADCRX0), FF18H (ADCRX1)
000000
ADCRXn
(n = 0, 1)
Cautions 1. When writing to the A/D converter mode register 0 (ADM0), analog input channel specification
register (ADS), and A/D port configuration registers 0, 1 (ADPC0, ADPC1), the contents of
ADCRXn may become undefined. Read the conversion result following conversion completion
before writing to ADM0, ADS, ADPC0, and ADPC1. Using timing other than the above may cause
an incorrect conversion result to be read.
2. If data is read from ADCRXn, a wait cycle is generated. Do not read data from ADCRXn when the
peripheral hardware clock (f
PRS) is stopped. For details, refer to CHAPTER 31 CAUTIONS FOR
WAIT.
Remark n = 0, 1
(6) 8-bit A/D conversion result register L for TMXn synchronization (ADCRXnL)
ADCRXnL is an 8-bit register that holds the A/D conversion result when A/D conversion is started with the output of
16-bit timer Xn as the trigger.
The lower 8 bits of the 10-bit resolution are stored in ADCRX0L if A/D conversion is performed with the output of 16-
bit timer X0 as the trigger or in ADCRX1L if A/D conversion is performed with the output of 16-bit timer X1 as the
trigger.
ADCRXnL can be read by an 8-bit memory manipulation instruction.
Reset signal generation clears ADCRXnL to 00H.