Datasheet
78K0/Ix2 CHAPTER 11 A/D CONVERTER
R01UH0010EJ0500 Rev.5.00 373
Feb 28, 2012
(3) 8-bit A/D conversion result register L (ADCRL)
ADCRL is an 8-bit register that stores the A/D conversion result. The lower 8 bits of 10-bit resolution are stored.
ADCRL can be read by an 8-bit memory manipulation instruction.
Reset signal generation clears ADCRL to 00H.
Figure 11-6. Format of 8-Bit A/D Conversion Result Register L (ADCRL)
Symbol
ADCRL
Address: FF08H After reset: 00H R
76543210
Cautions 1. When writing to the A/D converter mode register 0 (ADM0), analog input channel specification
register (ADS), and A/D port configuration registers 0, 1 (ADPC0, ADPC1), the contents of ADCRL
may become undefined. Read the conversion result following conversion completion before
writing to ADM0, ADS, ADPC0, and ADPC1. Using timing other than the above may cause an
incorrect conversion result to be read.
2. If data is read from ADCRL, a wait cycle is generated. Do not read data from ADCRL when the
peripheral hardware clock (f
PRS) is stopped. For details, refer to CHAPTER 31 CAUTIONS FOR
WAIT.
(4) 8-bit A/D conversion result register H (ADCRH)
ADCRH is an 8-bit register that stores the A/D conversion result. The higher 8 bits of 10-bit resolution are stored.
ADCRH can be read by an 8-bit memory manipulation instruction.
Reset signal generation clears ADCRH to 00H.
Figure 11-7. Format of 8-Bit A/D Conversion Result Register H (ADCRH)
Symbol
ADCRH
Address: FF0DH After reset: 00H R
76543210
Cautions 1. When writing to the A/D converter mode register 0 (ADM0), analog input channel specification
register (ADS), and A/D port configuration registers 0, 1 (ADPC0, ADPC1), the contents of ADCRH
may become undefined. Read the conversion result following conversion completion before
writing to ADM0, ADS, ADPC0, and ADPC1. Using timing other than the above may cause an
incorrect conversion result to be read.
2. If data is read from ADCRH, a wait cycle is generated. Do not read data from ADCRH when the
peripheral hardware clock (f
PRS) is stopped. For details, refer to CHAPTER 31 CAUTIONS FOR
WAIT.