Datasheet

78K0/Ix2 CHAPTER 11 A/D CONVERTER
R01UH0010EJ0500 Rev.5.00 370
Feb 28, 2012
Table 11-2. A/D Conversion Time Selection (1/2)
(1) 4.0 V  AVREF  5.5 V
A/D Converter Mode Register 0
(ADM0)
Conversion Time Selection
FR2 FR1 FR0 LV1 LV0
Mode
fPRS = 4 MHz fPRS = 8 MHz fPRS = 10 MHz
f
PRS = 20 MHz
(when using
PLL)
Conversion
Clock (fAD)
0 0 0 264/fPRS 66.0  s 33.0  s 26.4  s 13.2  s fPRS/12
0 0 1 176/fPRS 44.0  s 22.0  s 17.6  s 8.8  s fPRS/8
0 1 0 132/fPRS 33.0  s 16.5  s 13.2  s 6.6  s fPRS/6
0 1 1 88/fPRS 22.0  s 11.0  s 8.8  s fPRS/4
1 0 0 66/fPRS 16.5  s 8.25  s 6.6  s
Setting
prohibited
f
PRS/3
1 0 1 44/fPRS 11.0  s Setting prohibited fPRS/2
1 1 0 33/fPRS 8.25  s Setting prohibited fPRS/1.5
1 1 1
0 0 Normal
22/fPRS Setting prohibited fPRS
1 0 0 66/fPRS 16.5  s 8.25  s 6.6  s 3.3  s fPRS/3
1 1 0
1 0
High-speed
1
33/fPRS 8.25  s 4.125  s 3.3  s
Setting
prohibited
fPRS/1.5
1 0 1 44/fPRS 11.0  s 5.5  s 4.4  s
Setting
prohibited
f
PRS/2
1 1 1
1 1
High-speed
2
22/f
PRS 5.5  s Setting prohibited fPRS
Other than above Setting prohibited
Cautions 1. When rewriting FR2 to FR0, LV1, and LV0 to other than the same data, stop A/D conversion once
(ADCS = 0) beforehand.
2. The above conversion time does not include clock frequency errors. Select conversion time,
taking clock frequency errors into consideration.
Remark f
PRS: Peripheral hardware clock frequency