Datasheet

78K0/Ix2 CHAPTER 11 A/D CONVERTER
R01UH0010EJ0500 Rev.5.00 366
Feb 28, 2012
11.2 Configuration of A/D Converter
The A/D converter includes the following hardware.
(1) ANI0 to ANI8 pins
These are the analog input pins of the 9-channel A/D converter. They input analog signals to be converted into digital
signals. Pins other than the one selected as the analog input pin can be used as I/O port pins.
Remark A/D converter analog input pins differ depending on products.
 78K0/IY2: ANI0, ANI1, ANI3 to ANI5
 78K0/IA2: ANI0 to ANI5
 78K0/IB2: ANI0 to ANI8
(2) AMPOUT, PGAIN pins (products with operational amplifier only)
AMPOUT is the output pin of operational amplifier.
PGAIN is the input pin of PGA (Programmable gain amplifier).
They function alternately as ANI1. The A/D converter can perform A/D conversion by selecting the output signal of
operational amplifier or PGA as the analog input source.
(3) Sample & hold circuit
The sample & hold circuit samples each of the analog input voltages sequentially sent from the input circuit, and
sends them to the A/D voltage comparator. This circuit also holds the sampled analog input voltage during A/D
conversion.
(4) Comparison voltage generator
The comparison voltage generator is connected between AV
REF and AVSS, and generates a voltage to be compared
with an analog input. The operation of the comparison voltage generator is enabled or disabled by using the ADCS
bit (bit 7 of the ADM0 register). The power consumption can be reduced by stopping the operation of the comparison
voltage generator when A/D conversion is not performed.
(5) A/D voltage comparator
The A/D voltage comparator compares the sampled voltage values with the output voltage of the comparison voltage
generator. The operation of the A/D voltage comparator is enabled or disabled by using the ADCE bit (bit 0 of the
ADM0 register). The power consumption can be reduced by stopping the operation of the A/D voltage comparator
when A/D conversion is not performed.
(6) Successive approximation register (SAR)
The SAR register is a 10-bit register that sets a result compared by the A/D voltage comparator, 1 bit at a time starting
from the most significant bit (MSB).
If data is set in the SAR register all the way to the least significant bit (LSB) (end of A/D conversion), the contents of
the SAR register (conversion results) are held in the A/D conversion result register (ADCR, ADCRH).
(7) 10-bit A/D conversion result register (ADCR)
The A/D conversion result is loaded from the successive approximation register to this register each time A/D
conversion is completed, and the ADCR register holds the A/D conversion result in its lower 10 bits (the higher 6 bits
are fixed to 0).