Datasheet

78K0/Ix2 CHAPTER 10 WATCHDOG TIMER
R01UH0010EJ0500 Rev.5.00 358
Feb 28, 2012
10.2 Configuration of Watchdog Timer
The watchdog timer includes the following hardware.
Table 10-1. Configuration of Watchdog Timer
Item Configuration
Control register Watchdog timer enable register (WDTE)
How the counter operation is controlled, overflow time, and window open period are set by the option byte.
Table 10-2. Setting of Option Bytes and Watchdog Timer
Setting of Watchdog Timer Option Byte (0080H)
Window open period Bits 6 and 5 (WINDOW1, WINDOW0)
Controlling counter operation of watchdog timer Bit 4 (WDTON)
Overflow time of watchdog timer Bits 3 to 1 (WDCS2 to WDCS0)
Remark For the option byte, refer to CHAPTER 24 OPTION BYTE.
Figure 10-1. Block Diagram of Watchdog Timer
Clock
input
controller
Reset
output
controller
Internal reset signal
Internal bus
Selector
17-bit
counter
Watchdog timer enable
register (WDTE)
Clear, reset control
WDTON of option
byte (0080H)
WINDOW1 and WINDOW0
of option byte (0080H)
Count clear
signal
WDCS2 to WDCS0 of
option byte (0080H)
Overflow
signal
CPU access signal
CPU access
error detector
Window size
determination
signal
f IL /2
2
7
/fIL to 2
10
/fIL,
2
12
/fIL, 2
14
/fIL,
2
15
/fIL, 2
17
/fIL