Datasheet

78K0/Ix2 CHAPTER 9 8-BIT TIMER H1
R01UH0010EJ0500 Rev.5.00 351
Feb 28, 2012
To control the carrier pulse output during a count operation, the NRZ1 and NRZB1 bits of the TMCYC1 register have
a master and slave bit configuration. The NRZ1 bit is read-only but the NRZB1 bit can be read and written. The
INTTM51 signal is synchronized with the 8-bit timer H1 count clock and is output as the INTTM5H1 signal. The
INTTM5H1 signal becomes the data transfer signal of the NRZ1 bit, and the NRZB1 bit value is transferred to the
NRZ1 bit. The timing for transfer from the NRZB1 bit to the NRZ1 bit is as shown below.
Figure 9-13. Transfer Timing
8-bit timer H1
count clock
TMHE1
INTTM51
INTTM5H1
NRZ1
NRZB1
RMC1
1
1
10
00
<1>
<2>
<3>
<1> The INTTM51 signal is synchronized with the count clock of the 8-bit timer H1 and is output as the INTTM5H1
signal.
<2> The value of the NRZB1 bit is transferred to the NRZ1 bit at the second clock from the rising edge of the
INTTM5H1 signal.
<3> Write the next value to the NRZB1 bit in the interrupt servicing program that has been started by the INTTM5H1
interrupt or after timing has been checked by polling the interrupt request flag. Write data to count the next time
to the CR51 register.
Cautions 1. Do not rewrite the NRZB1 bit again until at least the second clock after it has been rewritten, or
else the transfer from the NRZB1 bit to the NRZ1 bit is not guaranteed.
2. When the 8-bit timer/event counter 51 is used in the carrier generator mode, an interrupt is
generated at the timing of <1>. When the 8-bit timer/event counter 51 is used in a mode other
than the carrier generator mode, the timing of the interrupt generation differs.
Remark INTTM5H1 is an internal signal and not an interrupt source.