Datasheet

78K0/Ix2 CHAPTER 9 8-BIT TIMER H1
R01UH0010EJ0500 Rev.5.00 349
Feb 28, 2012
Figure 9-12. Operation Timing in PWM Output Mode (4/4)
(e) Operation by changing CMP11 (CMP11 = 02H 03H, CMP01 = A5H)
Count clock
8-bit timer
counter Hn
CMP01
TMHE1
INTTMH1
TOH1
(TOLEV1 = 0)
00H 01H 02H A5H 00H 01H 02H 03H A5H 00H 01H 02H 03H A5H 00H
<1>
<4>
<3>
<2>
CMP11
<6>
<5>
02H
A5H
03H02H (03H)
<2>’
80H
<1> The count operation is enabled by setting TMHE1 = 1. Start the 8-bit timer counter H1 by masking one count
clock to count up. At this time, PWM output outputs an inactive level.
<2> The CMP11 register value can be changed during timer counter operation. This operation is asynchronous to the
count clock.
<3> When the values of the 8-bit timer counter H1 and the CMP01 register match, the value of the 8-bit timer counter
H1 is cleared, an active level is output, and the INTTMH1 signal is output.
<4> If the CMP11 register value is changed, the value is latched and not transferred to the register. When the values
of the 8-bit timer counter H1 and the CMP11 register before the change match, the value is transferred to the
CMP11 register and the CMP11 register value is changed (<2>’).
However, three count clocks or more are required from when the CMP11 register value is changed to when the
value is transferred to the register. If a match signal is generated within three count clocks, the changed value
cannot be transferred to the register.
<5> When the values of the 8-bit timer counter H1 and the CMP11 register after the change match, an inactive level is
output. The 8-bit timer counter H1 is not cleared and the INTTMH1 signal is not generated.
<6> Clearing the TMHE1 bit to 0 during timer H1 operation sets the INTTMH1 signal to the default and PWM output to
an inactive level.