Datasheet
78K0/Ix2 CHAPTER 9 8-BIT TIMER H1
R01UH0010EJ0500 Rev.5.00 344
Feb 28, 2012
9.4.2 Operation as PWM output
In PWM output mode, a pulse with an arbitrary duty and arbitrary cycle can be output.
The 8-bit timer compare register 01 (CMP01) controls the cycle of timer output (TOH1). Rewriting the CMP01 register
during timer operation is prohibited.
The 8-bit timer compare register 11 (CMP11) controls the duty of timer output (TOH1). Rewriting the CMP11 register
during timer operation is possible.
The operation in PWM output mode is as follows.
PWM output (TOH1 output) outputs an active level and 8-bit timer counter H1 is cleared to 0 when 8-bit timer counter
H1 and the CMP01 register match after the timer count is started. PWM output (TOH1 output) outputs an inactive level
when 8-bit timer counter H1 and the CMP11 register match.
Setting
<1> Set each register.
Figure 9-11. Register Setting in PWM Output Mode
(i) Setting timer H mode register 1 (TMHMD1)
0 0/1 0/1 0/1 1 0 0/1 1
TMMD10 TOLEV1 TOEN1CKS11CKS12TMHE1
TMHMD1
CKS10 TMMD11
Timer output enabled
Default setting of timer output level
PWM output mode selection
Count clock (f
CNT
) selection
Count operation stopped
(ii) Setting CMP01 register
Compare value (N): Cycle setting
(iii) Setting CMP11 register
Compare value (M): Duty setting
Remark 00H CMP11 (M) < CMP01 (N) FFH
<2> The count operation starts when TMHE1 = 1.
<3> The CMP01 register is the compare register that is to be compared first after counter operation is enabled. When
the values of the 8-bit timer counter H1 and the CMP01 register match, the 8-bit timer counter H1 is cleared, an
interrupt request signal (INTTMH1) is generated, and an active level is output. At the same time, the compare
register to be compared with the 8-bit timer counter H1 is changed from the CMP01 register to the CMP11
register.
<4> When the 8-bit timer counter H1 and the CMP11 register match, an inactive level is output and the compare
register to be compared with the 8-bit timer counter H1 is changed from the CMP11 register to the CMP01
register. At this time, the 8-bit timer counter H1 is not cleared and the INTTMH1 signal is not generated.