Datasheet

78K0/Ix2 CHAPTER 8 8-BIT TIMER/EVENT COUNTER 51
R01UH0010EJ0500 Rev.5.00 326
Feb 28, 2012
(1) Timer clock selection register 51 (TCL51)
This register sets the count clock of 8-bit timer/event counter 51 and the valid edge of the TI51 pin input.
TCL51 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears TCL51 to 00H.
Figure 8-4. Format of Timer Clock Selection Register 51 (TCL51)
Address: FF8CH After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
TCL51 0 0 0 0 0 TCL512 TCL511 TCL510
Count clock selection TCL512 TCL511 TCL510
f
PRS =
2 MHz
fPRS =
5 MHz
fPRS =
10 MHz
f
PRS = 20
MHz (when
using PLL)
0 0 0 TI51 pin falling edge
Note
0 0 1 TI51 pin rising edge
Note
0 1 0 fPRS 2 MHz 5 MHz 10 MHz 20 MHz
0 1 1 fPRS/2 1 MHz 2.5 MHz 5 MHz 10 MHz
1 0 0 fPRS/2
4
125 kHz 312.5 kHz 625 kHz 1.25 MHz
1 0 1 fPRS/2
6
31.25 kHz 78.13 kHz 156.25 kHz 312.5 kHz
1 1 0 fPRS/2
8
7.81 kHz 19.53 kHz 39.06 kHz 78.13 kHz
1 1 1 TMH1 output
Note Do not start timer operation with the external clock from the TI51 pin when in the STOP mode.
Cautions 1. When rewriting TCL51 to other data, stop the timer operation beforehand.
2. Be sure to clear bits 3 to 7 to “0”.
Remark f
PRS: Peripheral hardware clock frequency