Datasheet

78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00
R01UH0010EJ0500 Rev.5.00 321
Feb 28, 2012
(9) Capture operation
(a) When valid edge of TI000 is specified as count clock
When the valid edge of TI000 is specified as the count clock, the capture register for which TI000 is specified as
a trigger does not operate correctly.
(b) Pulse width to accurately capture value by signals input to TI010 and TI000 pins
To accurately capture the count value, the pulse input to the TI000 and TI010 pins as a capture trigger must be
wider than two count clocks selected by PRM00 (refer to Figure 7-7).
(c) Generation of interrupt signal
The capture operation is performed at the falling edge of the count clock but the interrupt signals (INTTM000 and
INTTM010) are generated at the rising edge of the next count clock (refer to Figure 7-7).
(d) Note when CRC001 (bit 1 of capture/compare control register 00 (CRC00)) is set to 1
When the count value of the TM00 register is captured to the CR000 register in the phase reverse to the signal
input to the TI000 pin, the interrupt signal (INTTM000) is not generated after the count value is captured. If the
valid edge is detected on the TI010 pin during this operation, the capture operation is not performed but the
INTTM000 signal is generated as an external interrupt signal. Mask the INTTM000 signal when the external
interrupt is not used.
(10) Edge detection
(a) Specifying valid edge after reset
If the operation of the 16-bit timer/event counter 00 is enabled after reset and while the TI000 or TI010 pin is at
high level and when the rising edge or both the edges are specified as the valid edge of the TI000 or TI010 pin,
then the high level of the TI000 or TI010 pin is detected as the rising edge. Note this when the TI000 or TI010
pin is pulled up. However, the rising edge is not detected when the operation is once stopped and then enabled
again.
(b) Sampling clock for eliminating noise
The sampling clock for eliminating noise differs depending on whether the valid edge of TI000 is used as the
count clock or capture trigger. In the former case, the sampling clock is fixed to f
PRS. In the latter, the count clock
selected by PRM00 is used for sampling.
When the signal input to the TI000 pin is sampled and the valid level is detected two times in a row, the valid
edge is detected. Therefore, noise having a short pulse width can be eliminated (refer to Figure 7-7).
(11) Timer operation
The signal input to the TI000/TI010 pin is not acknowledged while the timer is stopped, regardless of the operation
mode of the CPU.
Remark f
PRS: Peripheral hardware clock frequency