Datasheet

78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00
R01UH0010EJ0500 Rev.5.00 318
Feb 28, 2012
7.6 Cautions for 16-Bit Timer/Event Counter 00
(1) Restrictions for each channel of 16-bit timer/event counter 00
Table 7-3 shows the restrictions for each channel.
Table 7-3. Restrictions for Each Channel of 16-Bit Timer/Event Counter 00
Operation Restriction
As interval timer
As square-wave output
Note
As external event counter

As clear & start mode entered by
TI000 pin valid edge input
Using timer output (TO00) is prohibited when detection of the valid edge of the TI010 pin is
used. (TOC00 = 00H)
As free-running timer

As PPG output
Note
0000H  CP010 < CR000  FFFFH
As one-shot pulse outputa
Note
Setting the same value to CR000 and CP010 is prohibited.
As pulse width measurement Using timer output (TO00) is prohibited (TOC00 = 00H)
Note 78K0/IB2 (30 pins) only
(2) Timer start errors
An error of up to one clock may occur in the time required for a match signal to be generated after timer start. This is
because counting TM00 is started asynchronously to the count pulse.
Figure 7-56. Start Timing of TM00 Count
0000H
Timer start
0001H 0002H 0003H 0004H
Count pulse
T
M00 count value
(3) Setting of CR000 and CR010 (clear & start mode entered upon a match between TM00 and CR000)
Set a value other than 0000H to CR000 and CR010 (TM00 cannot count one pulse when it is used as an external
event counter).