Datasheet

78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00
R01UH0010EJ0500 Rev.5.00 302
Feb 28, 2012
Figure 7-43. Example of Software Processing for PPG Output Operation
TM00 register
0000H
Operable bits
(TMC003, TMC002)
Compare register
(CR000)
Compare match interrupt
(INTTM000)
Compare register
(CR010)
Compare match interrupt
(INTTM010)
Timer output control bits
(TOE00, TOC004, TOC001)
TO00 output
M
11
M M M
N
N
N
00
<1>
N + 1
<2>
00
N
TMC003, TMC002 bits = 11
Register initial setting
PRM00 register,
CRC00 register,
TOC00 register
Note
,
CR000, CR010 registers,
port setting
Initial setting of these
registers is performed
before setting the
TMC003 and TMC002
bits.
Starts count operation
START
<1> Count operation start flow
TMC003, TMC002 bits = 00
The counter is initialized
and counting is stopped
by clearing the TMC003
and TMC002 bits to 00.
STOP
<2> Count operation stop flow
N + 1 N + 1
M + 1M + 1M + 1
Note Care must be exercised when setting TOC00. For details, refer to 7.3 (3) 16-bit timer output control
register 00 (TOC00).
Remark PPG pulse cycle = (M + 1)  Count clock cycle
PPG duty = (N + 1)/(M + 1)