Datasheet

78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00
R01UH0010EJ0500 Rev.5.00 300
Feb 28, 2012
Figure 7-42. Example of Register Settings for PPG Output Operation (1/2)
(a) 16-bit timer mode control register 00 (TMC00)
00001100
TMC003 TMC002 TMC001 OVF00
Clears and starts on match
between TM00 and CR000.
(b) Capture/compare control register 00 (CRC00)
00000000
CRC002 CRC001 CRC000
CR000 used as
compare register
CR010 used as
compare register
(c) 16-bit timer output control register 00 (TOC00)
0 0 0 1 0/1
LVR00LVS00TOC004OSPE00OSPT00 TOC001 TOE00
Enables TO00 output
11: Inverts TO00 output on
match between TM00
and CR000/CR010.
00: Disables one-shot pulse
output
Specifies initial value of
TO00 output F/F
0/1 1 1
(d) Prescaler mode register 00 (PRM00)
00000
3 2 PRM001 PRM000ES110 ES100 ES010 ES000
Selects count clock
0 0/1 0/1