Datasheet

78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00
R01UH0010EJ0500 Rev.5.00 299
Feb 28, 2012
7.4.6 PPG output operation (78K0/IB2 (30 pins) only)
A square wave having a pulse width set in advance by CR010 is output from the TO00 pin as a PPG (Programmable
Pulse Generator) signal during a cycle set by CR000 when bits 3 and 2 (TMC003 and TMC002) of 16-bit timer mode
control register 00 (TMC00) are set to 11 (clear & start upon a match between TM00 and CR000).
The pulse cycle and duty factor of the pulse generated as the PPG output are as follows.
 Pulse cycle = (Set value of CR000 + 1)  Count clock cycle
 Duty = (Set value of CR010 + 1) / (Set value of CR000 + 1)
Caution To change the duty factor (value of CR010) during operation, refer to 7.5.1 Rewriting CR010 during
TM00 operation.
Remarks 1. For the setting of I/O pins, refer to 7.3 (6) Port mode register 0 (PM0).
2. For how to enable the INTTM000 signal interrupt, refer to CHAPTER 18 INTERRUPT FUNCTIONS.
Figure 7-41. Block Diagram of PPG Output Operation
Timer counter
(TM00)
Clear
Output
controller
Note
Compare register
(CR010)
Match signal
Match signal
Interrupt signal
(INTTM000)
Interrupt signal
(INTTM010)
Compare register
(CR000)
Operable bits
TMC003, TMC002
Count clock
TO00 pin
Note
TO00 output
Note
Note 78K0/IB2 (30 pins) only