Datasheet

78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00
R01UH0010EJ0500 Rev.5.00 294
Feb 28, 2012
Figure 7-38. Timing Example of Free-Running Timer Mode
(CR000: Capture Register, CR010: Capture Register) (1/2)
(a) TOC00 = 13H, PRM00 = 50H, CRC00 = 05H, TMC00 = 04H
FFFFH
TM00 register
0000H
Operable bits
(TMC003, TMC002)
Capture trigger input
(TI000)
Capture register
(CR010)
Capture interrupt
(INTTM010)
Capture trigger input
(TI010)
Capture register
(CR000)
Capture interrupt
(INTTM000)
Overflow flag
(OVF00)
01
M
A
B
C
DE
N
S
P
Q
00
0 write clear 0 write clear 0 write clear 0 write clear
0000H
ABC
D
E
0000H
MN S
P
Q
This is an application example where the count values that have been captured at the valid edges of separate capture
trigger signals are stored in separate capture registers in the free-running timer mode.
The count value is captured to CR010 when the valid edge of the TI000 pin input is detected and to CR000 when the
valid edge of the TI010 pin input is detected.