Datasheet

78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00

R01UH0010EJ0500 Rev.5.00 292

Feb 28, 2012

Figure 7-36. Timing Example of Free-Running Timer Mode

(CR000: Compare Register, CR010: Capture Register)

 TOC00 = 13H, PRM00 = 10H, CRC00 = 04H, TMC00 = 04H

FFFFH

TM00 register

0000H

Operable bits

(TMC003, TMC002)

Capture trigger input

(TI000)

Compare register

(CR000)

Compare match interrupt

(INTTM000)

Capture register

(CR010)

Capture interrupt

(INTTM010)

TO00 output

Overflow flag

(OVF00)

0 write clear 0 write clear 0 write clear 0 write clear

0000H

MN S

This is an application example where a compare register and a capture register are used at the same time in the free-

running timer mode.

In this example, the INTTM000 signal is generated and the TO00 output level is reversed each time the count value of

TM00 matches the set value of CR000 (compare register). In addition, the INTTM010 signal is generated and the

count value of TM00 is captured to CR010 each time the valid edge of the TI000 pin is detected.