Datasheet

78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00
R01UH0010EJ0500 Rev.5.00 290
Feb 28, 2012
7.4.5 Free-running timer operation
When bits 3 and 2 (TMC003 and TMC002) of 16-bit timer mode control register 00 (TMC00) are set to 01 (free-running
timer mode), 16-bit timer/event counter 00 continues counting up in synchronization with the count clock. When it has
counted up to FFFFH, the overflow flag (OVF00) is set to 1 at the next clock, and TM00 is cleared (to 0000H) and
continues counting. Clear OVF00 to 0 by executing the CLR instruction via software.
The following three types of free-running timer operations are available.
 Both CR000 and CR010 are used as compare registers.
 One of CR000 or CR010 is used as a compare register and the other is used as a capture register.
 Both CR000 and CR010 are used as capture registers.
Remarks 1. For the setting of the I/O pins, refer to 7.3 (6) Port mode register 0 (PM0).
2. For how to enable the INTTM000 signal interrupt, refer to CHAPTER 18 INTERRUPT FUNCTIONS.
(1) Free-running timer mode operation
(CR000: compare register, CR010: compare register)
Figure 7-33. Block Diagram of Free-Running Timer Mode
(CR000: Compare Register, CR010: Compare Register)
Timer counter
(TM00)
Output
controller
Note
Compare register
(CR010)
Match signal
Match signal
Interrupt signal
(INTTM000)
Interrupt signal
(INTTM010)
Compare register
(CR000)
Operable bits
TMC003, TMC002
Count clock
TO00 pin
Note
TO00 output
Note
Note 78K0/IB2 (30 pins) only