Datasheet
78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00
R01UH0010EJ0500 Rev.5.00 288
Feb 28, 2012
Figure 7-31. Example of Register Settings in Clear & Start Mode Entered by TI000 Pin Valid Edge Input (2/2)
(d) Prescaler mode register 00 (PRM00)
0/1 0/1 0/1 0/1 0
3 2 PRM001 PRM000ES110 ES100 ES010 ES000
Count clock selection
(setting TI000 valid edge is prohibited)
00: Falling edge detection
01: Rising edge detection
10: Setting prohibited
11: Both edges detection
(setting prohibited when CRC001 = 1)
00: Falling edge detection
01: Rising edge detection
10: Setting prohibited
11: Both edges detection
0 0/1 0/1
(e) 16-bit timer counter 00 (TM00)
By reading TM00, the count value can be read.
(f) 16-bit capture/compare register 000 (CR000)
When this register is used as a compare register and when its value matches the count value of TM00, an
interrupt signal (INTTM000) is generated. The count value of TM00 is not cleared.
To use this register as a capture register, select either the TI000 or TI010 pin
Note
input as a capture trigger.
When the valid edge of the capture trigger is detected, the count value of TM00 is stored in CR000.
Note The timer output (TO00) cannot be used when detection of the valid edge of the TI010 pin is used.
(g) 16-bit capture/compare register 010 (CR010)
When this register is used as a compare register and when its value matches the count value of TM00, an
interrupt signal (INTTM010) is generated. The count value of TM00 is not cleared.
When this register is used as a capture register, the TI000 pin input is used as a capture trigger. When the valid
edge of the capture trigger is detected, the count value of TM00 is stored in CR010.