Datasheet

78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00

R01UH0010EJ0500 Rev.5.00 280

Feb 28, 2012

Figure 7-26. Timing Example of Clear & Start Mode Entered by TI000 Pin Valid Edge Input

(CR000: Compare Register, CR010: Capture Register) (2/2)

(b) TOC00 = 13H, PRM00 = 10H, CRC00 = 04H, TMC00 = 0AH, CR000 = 0003H

TM00 register

0000H

Operable bits

(TMC003, TMC002)

Capture & count clear input

(TI000 pin input)

Compare register

(CR000)

Compare match interrupt

(INTTM000)

Capture register

(CR010)

Capture interrupt

(INTTM010)

TO00 output

0003H

QPNM

0000H M

4444

NS PQ

This is an application example where the width set to CR000 (4 clocks in this example) is to be output from the TO00

pin when the count value has been captured & cleared.

The count value is captured to CR010, a capture interrupt signal (INTTM010) is generated, TM00 is cleared (to

0000H), and the TO00 output level is inverted when the valid edge of the TI000 pin is detected. When the count

value of TM00 is 0003H (four clocks have been counted), a compare match interrupt signal (INTTM000) is generated

and the TO00 output level is inverted.