Datasheet

78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00
R01UH0010EJ0500 Rev.5.00 279
Feb 28, 2012
(2) Operation in clear & start mode entered by TI000 pin valid edge input
(CR000: compare register, CR010: capture register)
Figure 7-25. Block Diagram of Clear & Start Mode Entered by TI000 Pin Valid Edge Input
(CR000: Compare Register, CR010: Capture Register)
Timer counter
(TM00)
Clear
Output
controller
Note
Edge
detector
Capture register
(CR010)
Capture signal
Match signal
Interrupt signal
(INTTM000)
Interrupt signal
(INTTM010)
TI000 pin
Compare register
(CR000)
Operable bits
TMC003, TMC002
Count clock
TO00 pin
Note
TO00 output
Note
Note 78K0/IB2 (30 pins) only
Figure 7-26. Timing Example of Clear & Start Mode Entered by TI000 Pin Valid Edge Input
(CR000: Compare Register, CR010: Capture Register) (1/2)
(a) TOC00 = 13H, PRM00 = 10H, CRC00 = 04H, TMC00 = 08H, CR000 = 0001H
TM00 register
0000H
Operable bits
(TMC003, TMC002)
Capture & count clear input
(TI000 pin input)
Compare register
(CR000)
Compare match interrupt
(INTTM000)
Capture register
(CR010)
Capture interrupt
(INTTM010)
TO00 output
0001H
10
QPNM
S
00
0000H M N S P Q
This is an application example where the TO00 output level is inverted when the count value has been captured &
cleared.
The count value is captured to CR010 and TM00 is cleared (to 0000H) when the valid edge of the TI000 pin is
detected. When the count value of TM00 is 0001H, a compare match interrupt signal (INTTM000) is generated, and
the TO00 output level is inverted.