Datasheet
78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00
R01UH0010EJ0500 Rev.5.00 274
Feb 28, 2012
Figure 7-21. Example of Register Settings in External Event Counter Mode (1/2)
(a) 16-bit timer mode control register 00 (TMC00)
00001100
TMC003 TMC002 TMC001 OVF00
Clears and starts on match
between TM00 and CR000.
(b) Capture/compare control register 00 (CRC00)
00000000
CRC002 CRC001 CRC000
CR000 used as
compare regist
er
(c) 16-bit timer output control register 00 (TOC00)
0 0 0 0/1 0/1
LVR00LVS00TOC004OSPE00OSPT00 TOC001 TOE00
0/1 0/1 0/1
0: Disables TO00 output
1: Enables TO00 output
00: Does not invert TO00 output on match
between TM00 and CR000/CR010.
01: Inverts TO00 output on match between
TM00 and CR000.
10: Inverts TO00 output on match between
TM00 and CR010.
11: Inverts TO00 output on match between
TM00 and CR000/CR010.
Specifies initial value of
TO00 output F/F
(d) Prescaler mode register 00 (PRM00)
0 0 0/1 0/1 0
3 2 PRM001 PRM000ES110 ES100 ES010 ES000
Selects count clock
(specifies valid edge of TI000
).
00: Falling edge detection
01: Rising edge detection
10: Setting prohibited
11: Both edges detection
011