Datasheet

78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00
R01UH0010EJ0500 Rev.5.00 273
Feb 28, 2012
7.4.3 External event counter operation
When bits 1 and 0 (PRM001 and PRM000) of the prescaler mode register 00 (PRM00) are set to 11 (for counting up
with the valid edge of the TI000 pin) and bits 3 and 2 (TMC003 and TMC002) of 16-bit timer mode control register 00
(TMC00) are set to 11, the valid edge of an external event input is counted, and a match interrupt signal indicating
matching between TM00 and CR000 (INTTM000) is generated.
To input the external event, the TI000 pin is used. Therefore, the timer/event counter cannot be used as an external
event counter in the clear & start mode entered by the TI000 pin valid edge input (when TMC003 and TMC002 = 10).
The INTTM000 signal is generated with the following timing.
 Timing of generation of INTTM000 signal (second time or later)
= Number of times of detection of valid edge of external event  (Set value of CR000 + 1)
However, the first match interrupt immediately after the timer/event counter has started operating is generated with the
following timing.
 Timing of generation of INTTM000 signal (first time only)
= Number of times of detection of valid edge of external event input  (Set value of CR000 + 2)
To detect the valid edge, the signal input to the TI000 pin is sampled during the clock cycle of f
PRS. The valid edge is
not detected until it is detected two times in a row. Therefore, a noise with a short pulse width can be eliminated.
Remarks 1. For the setting of I/O pins, refer to 7.3 (6) Port mode register 0 (PM0).
2. For how to enable the INTTM000 signal interrupt, refer to CHAPTER 18 INTERRUPT FUNCTIONS.
Figure 7-20. Block Diagram of External Event Counter Operation
16-bit counter (TM00)
CR000 register
Operable bits
TMC003, TMC002
Clear
Match signal
INTTM000 signal
Edge
detection
TI000 pin
Output
controller
Note
TO00 output
Note
TO00 pin
Note
f PRS
Note 78K0/IB2 (30 pins) only