Datasheet

78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00
R01UH0010EJ0500 Rev.5.00 271
Feb 28, 2012
Figure 7-18. Example of Register Settings for Square-Wave Output Operation
(a) 16-bit timer mode control register 00 (TMC00)
00001100
TMC003 TMC002 TMC001 OVF00
Clears and starts on match
between TM00 and CR000.
(b) Capture/compare control register 00 (CRC00)
00000000
CRC002 CRC001 CRC000
CR000 used as
compare register
(c) 16-bit timer output control register 00 (TOC00)
0 0 0 0 0/1
LVR00LVS00TOC004OSPE00OSPT00 TOC001 TOE00
Enables TO00 output.
Inverts TO00 output on match
between TM00 and CR000.
0/1 1 1
Specifies initial value of TO00 output F/F
(d) Prescaler mode register 00 (PRM00)
00000
3 2 PRM001 PRM000ES110 ES100 ES010 ES000
Selects count clock
0 0/1 0/1
(e) 16-bit timer counter 00 (TM00)
By reading TM00, the count value can be read.
(f) 16-bit capture/compare register 000 (CR000)
If M is set to CR000, the interval time is as follows.
 Square wave frequency = 1 / [2  (M + 1)  Count clock cycle]
Setting CR000 to 0000H is prohibited.
(g) 16-bit capture/compare register 010 (CR010)
Usually, CR010 is not used for the square-wave output function. However, a compare match interrupt
(INTTM010) is generated when the set value of CR010 matches the value of TM00.
Therefore, mask the interrupt request by using the interrupt mask flag (TMMK010).