Datasheet
78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00
R01UH0010EJ0500 Rev.5.00 260
Feb 28, 2012
Figure 7-6. Format of Capture/Compare Control Register 00 (CRC00)
Address: FFBCH After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
CRC00 0 0 0 0 0 CRC002 CRC001 CRC000
CRC002 CR010 operating mode selection
0 Operates as compare register
1 Operates as capture register
CRC001 CR000 capture trigger selection
0 Captures on valid edge of TI010 pin
Note 1
1 Captures on valid edge of TI000 pin by reverse phase
Note 2
The valid edge of the TI010 and TI000 pin is set by PRM00.
If ES001 and ES000 are set to 11 (both edges) when CRC001 is 1, the valid edge of the TI000 pin cannot
be detected.
CRC000 CR000 operating mode selection
0 Operates as compare register
1 Operates as capture register
If TMC003 and TMC002 are set to 11 (clear & start mode entered upon a match between TM00 and
CR000), be sure to set CRC000 to 0.
Notes 1. When CRC001 = 0, the capture operation of CR000 is not performed because the 78K0/IY2, 78K0/IA2, and
78K0/IB2 (32 pins) are not provided with the TI010 pin.
2. When the valid edge is detected from the TI010 pin, the capture operation is not performed but the
INTTM000 signal is generated as an external interrupt signal.
Caution To ensure that the capture operation is performed properly, the capture trigger requires a pulse two
cycles longer than the count clock selected by prescaler mode register 00 (PRM00).
Figure 7-7. Example of CR010 Capture Operation (When Rising Edge Is Specified)
Count clock
TM00
TI000
Rising edge detection
CR010
INTTM010
N − 3N − 2N − 1 N N + 1
N
Valid edge