Datasheet

78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00

R01UH0010EJ0500 Rev.5.00 259

Feb 28, 2012

Figure 7-5. Format of 16-Bit Timer Mode Control Register 00 (TMC00)

(1) 78K0/IY2, 78K0/IA2, 78K0/IB2 (32 pins)

Address: FFBAH After reset: 00H R/W

Symbol 7 6 5 4 3 2 1 <0>

TMC00 0 0 0 0 TMC003 TMC002 0 OVF00

(2) 78K0/IB2 (30 pins)

Address: FFBAH After reset: 00H R/W

Symbol 7 6 5 4 3 2 1 <0>

TMC00 0 0 0 0 TMC003 TMC002 TMC001 OVF00

TMC003 TMC002 Operation enable of 16-bit timer/event counter 00

0 0

Disables 16-bit timer/event counter 00 operation. Stops supplying operating clock.

Clears 16-bit timer counter 00 (TM00).

0 1 Free-running timer mode

1 0 Clear & start mode entered by TI000 pin valid edge input

Note

1 1 Clear & start mode entered upon a match between TM00 and CR000

TMC001 Condition to reverse timer output (TO00)

0  Match between TM00 and CR000 or match between TM00 and CR010

 Match between TM00 and CR000 or match between TM00 and CR010

 Trigger input of TI000 pin valid edge

OVF00 TM00 overflow flag

Clear (0) Clears OVF00 to 0 or TMC003 and TMC002 = 00

Set (1) Overflow occurs.

OVF00 is set to 1 when the value of TM00 changes from FFFFH to 0000H in all the operation modes (free-running

timer mode, clear & start mode entered by TI000 pin valid edge input, and clear & start mode entered upon a match

between TM00 and CR000).

It can also be set to 1 by writing 1 to OVF00.

Note The TI000 pin valid edge is set by bits 5 and 4 (ES001, ES000) of prescaler mode register 00 (PRM00).

(2) Capture/compare control register 00 (CRC00)

CRC00 is the register that controls the operation of CR000 and CR010.

Changing the value of CRC00 is prohibited during operation (when TMC003 and TMC002 = other than 00).

CRC00 can be set by a 1-bit or 8-bit memory manipulation instruction.

Reset signal generation clears CRC00 to 00H.