Datasheet

78K0/Ix2 CHAPTER 1 OUTLINE
R01UH0010EJ0500 Rev.5.00 14
Feb 28, 2012
1.5 Outline of Functions
(1/2)
78K0/IY2 78K0/IA2 78K0/IB2 Item
16 pins 20 pins 30 pins 32 pins
Flash memory
(self-programming
supported)
4 KB to 16 KB 8 KB and 16 KB
Internal
memory
High-Speed RAM
384 bytes to 768 bytes
512 bytes and 768 bytes
Memory space
64 KB
High-speed system
(crystal/ceramic
oscillation, external
clock input)
1 to 10 MHz: V
DD = 2.7 to 5.5 V
Main
Internal high-
speed oscillation
4 MHz± 2 % (T
A = –20 to +70C)
Note
, or 8 MHz ± 3 % (TA = –40 to +85C): VDD = 2.7 to 5.5 V
Internal low-speed
oscillation
30 kHz ± 10 %: V
DD = 2.7 to 5.5 V
Clock
Clock for 16-bit timers
X0 and X1
40 MHz (TYP.) (when using PLL)
General-purpose registers
8 bits × 32 registers (8 bits × 8 registers × 4 banks)
Instruction set
• 8-bit operation, 16-bit operation
• Multiply/divide (8 bits  8 bits, 16 bits  8 bits)
• Bit manipulate (set, reset, test, and Boolean operation)
• BCD adjust, etc.
I/O ports
12
(CMOS I/O: 9, CMOS
input: 3)
16
(CMOS I/O: 13, CMOS
input: 3)
25
(CMOS I/O: 22, CMOS
input: 3)
23
(CMOS I/O: 20, CMOS
input: 3)
16 bits (TMx)
2 ch (PWM output: 4)
16 bits (TM0)
1 ch (capture input: 1)
1 ch (PPG output: 1,
capture input: 2)
1 ch (capture input: 1)
8 bits (TM51)
1 ch
8 bits (TMH1)
1 ch (PWM output: 1)
Timer
Watchdog (WDT)
1 ch
Note When using a 4 MHz clock, operation at 20 MHz is possible by using PLL.