Datasheet

78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00
R01UH0010EJ0500 Rev.5.00 256
Feb 28, 2012
Operation enabled
(other than 00)
TM00 register
Timer counter clear
Interrupt signal
is not generated
Interrupt signal
is generated
Timer operation enable bit
(TMC003, TMC002)
Interrupt request signal
Compare register set value
(0000H)
Operation
disabled (00)
Remarks 1. N: CR000 register set value, M: CR010 register set value
2. For details of the operation enable bits (bits 3 and 2 (TMC003 and TMC002)), refer to 7.3 (1) 16-bit timer
mode control register 00 (TMC00).