Datasheet
78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00
R01UH0010EJ0500 Rev.5.00 255
Feb 28, 2012
Figure 7-4. Format of 16-Bit Timer Capture/Compare Register 010 (CR010)
CR010
FF15H FF14H
Address: FF14H, FF15H After reset: 0000H R/W
1514131211109876543210
(i) When CR010 is used as a compare register
The value set in CR010 is constantly compared with the TM00 count value, and an interrupt request signal
(INTTM010) is generated if they match.
Caution CR010 does not perform the capture operation when it is set in the comparison mode, even if a
capture trigger is input to it.
(ii) When CR010 is used as a capture register
The count value of TM00 is captured to CR010 when a capture trigger is input.
It is possible to select the valid edge of the TI000 pin as the capture trigger. The TI000 pin valid edge is set by
PRM00.
(iii) Setting range when CR000 or CR010 is used as a compare register
When CR000 or CR010 is used as a compare register, set it as shown below.
Operation CR000 Register Setting Range CR010 Register Setting Range
Operation as interval timer
Operation as square-wave output
Note 1
Operation as external event counter
0000H < N FFFFH 0000H
Note 2
M FFFFH
Normally, this setting is not used. Mask the
match interrupt signal (INTTM010).
Operation in the clear & start mode
entered by TI000 pin valid edge input
Operation as free-running timer
0000H
Note 2
N FFFFH 0000H
Note 2
M FFFFH
Operation as PPG output
Note 1
M < N FFFFH 0000H
Note 2
M < N
Operation as one-shot pulse output
Note 1
0000H
Note 2
N FFFFH (N M) 0000H
Note 2
M FFFFH (M N)
Notes 1. 78K0/IB2 (30 pins) only
2. When 0000H is set, a match interrupt immediately after the timer operation does not occur and timer output
is not changed, and the first match timing is as follows. A match interrupt occurs at the timing when the
timer counter (TM00 register) is changed from 0000H to 0001H.
When the timer counter is cleared due to overflow
When the timer counter is cleared due to TI000 pin valid edge (when clear & start mode is entered by
TI000 pin valid edge input)
When the timer counter is cleared due to compare match (when clear & start mode is entered by match
between TM00 and CR000 (CR000 = other than 0000H, CR010 = 0000H))