Datasheet
78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1
R01UH0010EJ0500 Rev.5.00 249
Feb 28, 2012
6.7.3 High-impedance output control circuit setting procedure
(1) Transitioning to the high-impedance output state by detecting the valid edge of the INTP0 input or the output
of comparators 0 to 2
<1> Set the HIZTRS1, HSTRS0, and HIZPTS3 to HIZPTS0 bits (select the trigger source and the high-impedance
target pin).
<2> Set the HZA0DCM0, HZA0DCN0, and HZA0DCP0 bits (select the high-impedance state release condition and
valid edge).
<3> Set (1) the HIZTREN0 bit (enable the input of the trigger signal).
<4> Set (1) the HZA0DCE0 bit (enable the high-impedance output control operation).
(2) Changing the settings after enabling the high-impedance output control operation
<1> Clear (0) the HZA0DCE0 bit (disable the high-impedance output control operation).
<2> Clear (0) the HIZTREN0 bit (disable the input of the trigger signal).
<3> Change the HIZTRS1, HSTRS0, and HIZPTS3 to HIZPTS0 bits (change the trigger source and high-
impedance target pin).
<4> Set the HZA0DCM0, HZA0DCN0, and HZA0DCP0 bits (select the high-impedance state release condition and
valid edge).
<5> Set (1) the HIZTREN0 bit (re-enable the input of the trigger signal).
<6> Set (1) the HZA0DCE0 bit (re-enable the high-impedance output control operation).
(3) Restarting output while a pin is in the high-impedance output state
The impedance output state can be released only when the valid edge of the trigger to be used is detected when
HZA0DCM0 = 1 and the HZA0DCC0 bit is set (1) after the trigger signal is set to the inactive level.
When HZA0DCM0 = 0, the impedance output state is released when the HZA0DCC0 bit is set (1), regardless of the
level of the trigger signal.
(a) HZA0DCM0 = 1
<1> Set (1) the HZA0DCC0 bit (generate the instruction signal releasing the high-impedance state).
<2> Read the HZA0DCF0 bit and check the flag status.
<3> If HZA0DCF0 = 1, return to operation <1>. The level of the trigger signal must be checked.
If HZA0DCF0 = 0, pin output can be performed.
(b) HZA0DCM0 = 0
Set (1) the HZA0DCC0 bit (the instruction signal releasing the high-impedance state is generated -> pin output
can be performed).
Caution If the trigger signal is at the inactive level and the timing of setting (1) the HZA0DCC0 bit and the
timing at which the valid edge of the trigger signal is detected match, setting (1) the HZA0DCC0
bit may be given precedence.