Datasheet

78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1
R01UH0010EJ0500 Rev.5.00 248
Feb 28, 2012
Figure 6-58. Format of High-impedance Output Function Control Register 0 (HZA0CTL0) (2/2)
HZA0DCT0
Notes1 to 4
High-impedance output trigger bit
0 Does not operate.
1 Sets target pin to high-impedance output state and sets (1) HZA0DCF0 bit.
HZA0DCC0
Notes2 to 6
High-impedance output control clear bit
0 Does not operate.
1 Enables output of target pin and clears (0) HZA0DCF0 bit.
HZA0DCF0 High-impedance output state flag
0 Output of target pin is enabled.
 Clears (0) when HZA0DCE0 = 0.
 Clears (0) when HZA0DCC0 = 1.
1 Target pin is in high-impedance output state.
 Sets (1) when HZA0DCT0 = 1.
 Sets (1) when edge indicating abnormality is detected from trigger signal (when valid edge set by
HZA0DCN0 and HZA0DCP0 bits is detected).
Notes 1. This is invalid even if the HZA0DCT0 bit is set (1), when an edge indicating an abnormality is detected from
the trigger signal to be used (when the valid edge set by the HZA0DCN0 and HZA0DCP0 bits is detected).
2. This is invalid even if the HZA0DCT0 and HZA0DCC0 bits are set (1) when HZA0DCE0 = 0.
3. 0 is read from the HZA0DCT0 and HZA0DCC0 bits.
4. Do not simultaneously set the HZA0DCT0 and HZA0DCC0 bits to 1.
5. If the HZA0DCC0 bit is set (1) when HZA0DCM0 = 0, the high-impedance output state of the target pin will
be released regardless of the signal to be used as the trigger.
6. This is invalid even if the HZA0DCC0 bit is set (1), when an edge indicating an abnormality is detected from
the signal to be used as the trigger (when the valid edge set by the HZA0DCN0 and HZA0DCP0 bits is
detected) when HZA0DCM0 = 1.