Datasheet

78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1
R01UH0010EJ0500 Rev.5.00 247
Feb 28, 2012
(3) High-impedance output function control register 0 (HZA0CTL0)
HZA0CTL0 is a register that controls the high-impedance state of the output buffers.
HZA0CTL0 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears HZA0CTL0 to 00H.
Figure 6-58. Format of High-impedance Output Function Control Register 0 (HZA0CTL0) (1/2)
Address: FF78H After reset: 00H R/W
Note1
Symbol <7> <6> <5> <4> <3> <2> 1 <0>
HZA0CTL0 HZA0DCE0 HZA0DCM0 HZA0DCN0 HZA0DCP0 HZA0DCT0 HZA0DCC0 0 HZA0DCF0
HZA0DCE0 High-impedance output control
0 Disables high-impedance output control operation. Output of target pin can be performed.
1 Enables high-impedance output control operation
HZA0DCM0
Note2
Condition of releasing high-impedance state by HZA0DCC0 bit
0 HZA0DCC0 bit setting is valid regardless of signal to be used.
1 HZA0DCC0 bit setting is invalid while signal to be used holds abnormal detection level (active level).
HZA0DCN0
Note2
HZA0DCP0
Note2
Valid-edge specification during high-impedance control
Notes 3, 4
0 0 No valid edge (disables setting (1) HZA0DCF0 bit by INTP0 or comparator output).
0 1 Enables rising edge of signal to be used (abnormal detection at rising edge).
1 0 Enables falling edge of signal to be used (abnormal detection at falling edge).
1 1 Setting prohibited
Notes 1. Bit 0 is read only.
2. The HZA0DCM0, HZA0DCN0, and HZA0DCP0 bits should be rewritten when HZA0DCE0 = 0.
3. For the valid edge for INTP0, and INTCMP0 to INTCMP2, see 18. 3 (5) External interrupt rising edge
enable registers 0, 1 (EGPCTL0, EGPCTL1), external interrupt falling edge enable registers 0, 1
(EGNCTL0, EGNCTL1).
4. High-impedance output control will be performed if a valid edge is detected after the high-impedance output
control operation is enabled (HZA0DCE0 = 1). Consequently, if the trigger signal to be used is at the active
level when the operation is enabled, high-impedance output control will not be performed.