Datasheet

78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1
R01UH0010EJ0500 Rev.5.00 243
Feb 28, 2012
(b) Priority of interlocking modes 1 and 3
If interlocking modes 1 and 3 occur at the same time, or if interlocking mode 3 occur while the timer is being
reset in interlocking mode 1, interlocking mode 1 has priority and interlocking mode 3 is invalid.
Figure 6-53. Priority When Interlocking Mode 1 Conflicts with Interlocking Mode 3
D 0
D 0
D 1
D 1
D 1
D 2
D 3
D 0
D 2
D 0
D 2
FFFFH
16-bit timer counter Xn
0000H
TOXn0 pin output
(TXnTOL0 = 0)
TOXn1 pin output
(TXnTOL1 = 0)
Comparator output or
INTP0 input
(Interlocking mode 1)
Comparator output or
INTP0 input
(Interlocking mode 3)
INTTMXn signal
Count
clear
Count
clear
Timer
output
reset
Timer
output
reset
Timer
output
reset
Timer
output
reset
Interlocking mode 1 has priority
(c) Priority of interlocking modes 2 and 3
If interlocking modes 2 and 3 occur at the same time, interlocking mode 2 has priority and interlocking
mode 3 is invalid.
Figure 6-54. Priority When Interlocking Mode 2 Conflicts with Interlocking Mode 3
D0
D0
D1
D1
D1
D2
D3
D0
D2
D0
D2
FFFFH
16-bit timer counter Xn
0000H
TOXn0 pin output
(TXnTOL0 = 0)
TOXn1 pin output
(TXnTOL1 = 0)
Comparator output or
INTP0 input
(Interlocking mode 2)
Comparator output or
INTP0 input
(Interlocking mode 3)
INTTMXn signal
Interlocking mode 2 has priority
If interlocking mode 2 is triggered by the detection of an edge while the timer
is being reset in interlocking mode 3, interlocking mode 2 is valid.
Count
restart
Count
restart
Timer
output
reset
Timer
output
reset
Timer
output
reset
Count
continue
Remark n = 0, 1