Datasheet

78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1
R01UH0010EJ0500 Rev.5.00 242
Feb 28, 2012
(4) Priority when multiple interlocking modes occur
If multiple interlocking modes have been specified for TMX0 or TMX1, the priority order is as follows:
Interlocking mode 1 > Interlocking mode 2 > Interlocking mode 3
(a) Priority of interlocking modes 1 and 2
If interlocking modes 1 and 2 occur at the same time, or if interlocking mode 2 occur while the timer is being
reset in interlocking mode 1, interlocking mode 1 has priority and interlocking mode 2 is invalid.
Figure 6-52. Priority When Interlocking Mode 1 Conflicts with Interlocking Mode 2
Interlocking mode 1 has priority
D
0
D 0
D 1
D 1
D 1
D 2
D 3
D 0
D 2
D 0
D 2
Count
clear
Count
clear
Timer
output
reset
Timer
output
reset
Timer
output
reset
Timer
output
reset
FFFFH
16-bit timer counter Xn
0000H
TOXn0 pin output
(TXnTOL0 = 0)
TOXn1 pin output
(TXnTOL1 = 0)
Comparator output or
INTP0 input
(Interlocking mode 1)
Comparator output or
INTP0 input
(Interlocking mode 2)
INTTMXn signal
Remark n = 0, 1