Datasheet

78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1
R01UH0010EJ0500 Rev.5.00 238
Feb 28, 2012
(2) Interlocking mode 2 (timer restart mode)
This mode restarts the corresponding timer when the rising edge of the comparators 0 to 2 outputs or the INTP0
input is detected.
Figure 6-48. Example of Register Settings for Interlocking mode 2 (timer restart mode)
 Using CMP2 and INTP0 as triggers
0TX0CTL3 0 0 0 1 0 1 0
Uses CMP2 as trigger
Uses INTP0 as trigger
Remark When interlocking the timers with either CMP2 or INTP0, set all bits of CMP2 or INTP0, whichever is
not used, to 0.
 Using CMP0 and CMP1 as triggers
0TX0CTL4 0 0/1 1 0 0/1 1 0
TX0CMP0RPTX0CMP1RP
Uses CMP0 as trigger
TX0CMP0RP = 0: Interlocks with TMX0
TX0CMP0RP = 1: Interlocks with TMX1
Uses CMP1 as trigger
TX0CMP1RP = 0: Interlocks with TMX0
TX0CMP1RP = 1: Interlocks with TMX1
Remark When interlocking the timers with either CMP0 or CMP1, set all bits of CMP0 or CMP1, whichever is
not used, to 0.