Datasheet

78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1
R01UH0010EJ0500 Rev.5.00 236
Feb 28, 2012
Figure 6-44. Block Diagram of 16-Bit Timer X1 Output Configuration
TOTX1C0
TOTX1C1
TOTX1C2
INTTMX1
TOTX1C3
TOX10/P33
TOX11/P34
PM33
PM34
Level
controller
Level
controller
Output latch
(P33)
Output latch
(P34)
Comparator 0 output
Comparator 1 output
Mode
selector
Mode
selector
Timer clear
controller
Timer counter clear signal
Capture trigger signal
Note1
Note2
Note1
Note2
Figure 6-45. Block Diagram of 16-Bit Timers X0 and X1 Output Configuration
TOTX1C0
TOTX1C1
TOTX1C2
INTTMX0
TOTX1C3
INTTMX1
TOTX0C0
TOTX0C1
TOTX0C2
TOTX0C3
TOX00/P31
TOX01/P32
PM32
PM31
TOX10/P33
TOX11/P34
PM34
PM33
TOH1
(from TMH1)
INTP0
Output latch (P31)
Output latch (P32)
Output latch (P33)
Output latch (P34)
Output gate
control circuit
Output gate
control circuit
Output gate
control circuit
Output gate
control circuit
Comparator 2 output
Mode
selector
Timer counter clear signal
Capture trigger signal
Level
controller
Timer clear
controller
Level
controller
Level
controller
Level
controller
Note1
Note2
Note1
Note1
Note1
Notes 1. Timer output is controlled by the level controller according to the value of the compare register and the
mode selector output.
2. Resetting timer output (interlocking modes 1 and 3) and clearing the timer counter (interlocking modes 1
and 2) are controlled by the mode selector according to the comparator output or INTP0 input.
The modes controlled by comparator output or external interrupt input (INTP0) are described below.
(1) Interlocking mode 1 (timer reset mode)
This mode sets the output of the corresponding timer to the reset state while the output of comparators 0 to 2 or
INTP0 input is at high level, and restarts the timer when the detection signal is stopped.