Datasheet
78K0/Ix2 CHAPTER 1 OUTLINE
R01UH0010EJ0500 Rev.5.00 11
Feb 28, 2012
1.4.2 78K0/IA2
PORT 0
P00
PORT 2
P20 to P25
6
PORT 3
P31 to P34
POWER ON CLEAR/
LOW VOLTAGE
INDICATOR
POC/LVI
CONTROL
RESET CONTROL
PORT 6
P60, P61
2
P121, P122, P125
3
PORT 12
SYSTEM
CONTROL
RESET/P125
X1/P121
X2/EXCLK/P122
INTERRUPT
CONTROL
6
A/D CONVERTER
AVREF
INTP0/P00
SERIAL
INTERFACE IICA
SDAA0/P61
SCLA0/P60
INTP2/P31, INTP3/P32,
INTP4/P34
INTERNAL
HIGH-SPEED
RAM
78K/0
CPU
CORE
FLASH
MEMORY
8-bit TIMER
H1
<TOH1>/P00
<TOH1>/P34
WATCHDOG TIMER
16-bit TIMER/
EVENT COUNTER 00
TI000/P00
<TI000>/P121
<INTP0>/P121
RxD6/P61 (LINSEL)
TxD6/P60 (LINSEL)
RxD6/P61
TxD6/P60
SERIAL
INTERFACE UART6
LINSEL
ON-CHIP DEBUG
INTERNAL
HIGH-SPEED
OSCILLATOR
INTERNAL
LOW-SPEED
OSCILLATOR
OPERATIONAL
AMPLIFIER
Note
AMP+
Note
/P22
AMP-
Note
/P20
AMPOUT
Note
/P21
4
ANI0/P20 to ANI5/P25
TOOLC0/X1, TOOLC1/P31
TOOLD0/X2, TOOLD1/P32
3
VOLTAGE
REGULATOR
REGC
8-bit TIMER/
EVENT COUNTER 51
<TI51>/P00
<TI51>/P34
VSSVDD
COMPARATOR
3
CMP0+/P24,
CMP1+/P25,
CMP2+/P23
16-bit TIMER
X0
TOX01/P32
TOX00/P31
16-bit TIMER
X1
TOX11/P34
TOX10/P33
PROGRAMMABLE
GAIN AMPLIFIER
Note
PGAIN
Note
/P21
Note
PD78F0753, 78F0754 (products with operational amplifier) only
Cautions 1. V
SS functions alternately as the ground potential of the A/D converter. Be sure to connect VSS to
a stabilized GND (= 0 V).
2. Connect the REGC pin to V
SS via a capacitor (0.47 to 1
F).
3. ANI0/P20/AMP-, ANI1/P21/AMPOUT/PGAIN, ANI2/P22/AMP+, ANI3/P23/CMP2+, ANI4/P24/CMP0+,
and ANI5/P25/CMP1+ are set in the analog input mode after release of reset.
4. RESET/P125 immediately after release of reset is set in the external reset input.
Remark Functions in angle brackets < > can be assigned by setting the input switch control register (MUXSEL).