Datasheet
78K0/Ix2 CHAPTER 1 OUTLINE
R01UH0010EJ0500 Rev.5.00 10
Feb 28, 2012
1.4 Block Diagram
1.4.1 78K0/IY2
PORT 2
PORT 3
POWER ON CLEAR/
LOW VOLTAGE
INDICATOR
POC/LVI
CONTROL
RESET CONTROL
P121, P122, P125
3
PORT 12
SYSTEM
CONTROL
RESET/P125
X1/P121
X2/EXCLK/P122
COMPARATOR
A/D CONVERTER
AVREF
INTERNAL
HIGH-SPEED
RAM
78K/0
CPU
CORE
FLASH
MEMORY
8-bit TIMER
H1
8-bit TIMER
51
WATCHDOG TIMER
16-bit TIMER/
EVENT COUNTER 00
ON-CHIP DEBUG
INTERNAL
HIGH-SPEED
OSCILLATOR
INTERNAL
LOW-SPEED
OSCILLATOR
PROGRAMMABLE
GAIN AMPLIFIER
Note
PGAIN
Note
/P21
<TI000>/P121
<TI000>/P125
P20, P21, P23 to P2
5
5
P31 to P34
4
5
<TOH1>/P34
INTERRUPT
CONTROL
<INTP0>/P121
<INTP0>/P125
<TI51>/P34
ANI0/P20, ANI1/P21,
A
NI3/P23 to ANI5/P25
3
CMP0+/P24,
CMP1+/P25,
CMP2+/P23
3
INTP2/P31,
INTP3/P32,
INTP4/P34
16-bit TIMER
X0
TOX01/P32
TOX00/P31
16-bit TIMER
X1
TOX11/P34
TOX10/P33
VOLTAGE
REGULATOR
REGC
VSSVDD
TOOLC0/X1, TOOLC1/P3
1
TOOLD0/X2, TOOLD1/P3
2
Note
PD78F0750, 78F0751, 78F0752 (products with operational amplifier) only
Cautions 1. V
SS functions alternately as the ground potential of the A/D converter. Be sure to connect VSS to
a stabilized GND (= 0 V).
2. Connect the REGC pin to V
SS via a capacitor (0.47 to 1
F).
3. ANI0/P20, ANI1/P21/PGAIN, ANI3/P23/CMP2+, ANI4/P24/CMP0+, and ANI5/P25/CMP1+ are set in
the analog input mode after release of reset.
4. RESET/P125 immediately after release of reset is set in the external reset input.
Remark Functions in angle brackets < > can be assigned by setting the input switch control register (MUXSEL).