Datasheet

78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1
R01UH0010EJ0500 Rev.5.00 211
Feb 28, 2012
Figure 6-22. Example of Register Settings for A/D Conversion Start Timing Signal Output
(a) 16-bit timer Xn operation control register 0 (TXnCTL0)
0 0 0 0 0/1 0/1 0/11
TXnCKS2 TXnCKS1 TXnCKS0 TXnTMC
Selects count clock
Starts timer count operation
(b) 16-bit timer Xn operation control register 2 (TXnCTL2)
00000010
TXnADEN TXnCCS
TXnCCR0 used as compare register.
Enable generates
A/D conversion synchronization trigger.
(c) 16-bit timer X0 operation control register 1 (TX0CTL1)
00000000/1
TX0INTPST TX0PWMCE TX0PWM TX0PWMCINV
Select target compare register of INTTMX0
0: INTTMX0 is generated upon match of counter and TX0CR1 register
1: INTTMX0 is generated upon match of counter and TX0CR3 register
(d) 16-bit timer X1 operation control register 1 (TX1CTL1)
0 0 0 0 0/1 0 0/1 0/1
TX1PWM TX1MD1 TX1MD0TX1PWMCE
Select target compare register of INTTMX1
0: INTTMX1 is generated upon match of counter and TX1CR1 register
1: INTTMX1 is generated upon match of counter and TX1CR3 register
Operation mode setting
00 : TMX1-only start mode
(e) 16-bit timer Xn compare register m (TXnCRm)
If N is set to TXnCRm, the A/D conversion synchronization trigger generation period is as follows.
• The A/D conversion synchronization trigger generation period = (N + 1) × Count clock cycle
Setting TXnCRm to 0000H is prohibited.
(f) 16-bit timer Xn capture/compare register 0 (TXnCCR0)
If M is set to TXnCCR0, the A/D conversion synchronization trigger is generated at a time later than counting
0000H only for M.
Remarks 1. m = 1, 3
n = 0, 1
2. For details of A/D conversion in combination with 16 bit timer X0 or X1, refer to 11.4.2 Basic operation
of A/D converter (timer trigger mode).