Datasheet

78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1
R01UH0010EJ0500 Rev.5.00 210
Feb 28, 2012
(2) A/D conversion start timing signal output
If bit 1 (TXnADEN) of the 16-bit timer Xn operation control register 2 (TXnCTL2) is set to 1, the generation of the A/D
conversion synchronization trigger is enabled. If bit 7 (TXnTMC) of the 16-bit timer Xn operation control register 0
(TXnCTL0) is set to 1, the count operation is started in synchronization with the count clock.
When the value of the 16-bit timer counter Xn (TMXn) later matches the value of TXnCCR0, the A/D conversion
synchronization trigger is generated. When the value of TMXn matches the value of TXnCRm, TMXn is cleared to 0000H.
To output the A/D conversion start timing signal, satisfy the relationship between TXnCCR0 and TXnCRm as follows.
 TXnCCR0 < TXnCRm
If this relationship is not satisfied, the A/D conversion trigger is not generated.
Remarks 1. For details of the A/D conversion in combination with 16 bit timer X0 or X1, refer to 11.4.2 Basic
operation of A/D converter (timer trigger mode).
2. m = 1, 3
n = 0, 1
Figure 6-21. Basic Timing Example of A/D Conversion Start Timing Signal Output
16-bit timer counter Xn
N
1
1
0
0
N N N N
A/D conversion synchronization trigger
Compare register
(TXnCRm)
Operable bits
(TXnTMC)
A/D conversion synchronization
trigger enable bits (TXnADEN)
0000H
M
Compare register
(TXnCCR0)
Compare match interrupt
(INTTMXn)
M M
M
M
Remark m = 1, 3
n = 0, 1