Datasheet

78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1
R01UH0010EJ0500 Rev.5.00 208
Feb 28, 2012
Figure 6-19. Example of Register Settings for Interval Timer Operation
(a) 16-bit timer Xn operation control register 0 (TXnCTL0)
0 0 0 0 0/1 0/1 0/11
TXnCKS2 TXnCKS1 TXnCKS0 TXnTMC
Selects count clock
Starts timer count operation
(b) 16-bit timer X0 operation control register 1 (TX0CTL1)
00000/1000
TX0INTPST TX0PWMTX0PWMCE TX0PWMCINV
Select target compare register of INTTMX0
0 : INTTMX0 is generated upon match of counter and TX0CR1 register
1 : INTTMX0 is generated upon match of counter and TX0CR3 register
(c) 16-bit timer X1 operation control register 1 (TX1CTL1)
0 0 0 0 0/1 0 0/1 0/1
TX1PWM TX1MD1 TX1MD0TX1PWMCE
Select target compare register of INTTMX1
0 : INTTMX1 is generated upon match of counter and TX1CR1 register
1 : INTTMX1 is generated upon match of counter and TX1CR3 register
Operation mode setting
00 : TMX1-only start mode
01 : TMX0 and TMX1 Synchronous start mode
10 : TMX0 and TMX1 Synchronous start/clear mode
11 : Setting prohibited
(d) 16-bit timer Xn capture/compare register m (TXnCRm)
If N is set to TXnCRm, the interval time is as follows.
• Interval time = (N + 1) × Count clock cycle
Setting TXnCRm to 0000H is prohibited.
Remark m = 1, 3
n = 0, 1