Datasheet
78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1
R01UH0010EJ0500 Rev.5.00 207
Feb 28, 2012
6.4 Operation of 16-Bit Timer/Event Counter 00
(1) Interval timer operation
If bit 7 (TXnTMC) of the 16-bit timer Xn operation control register 0 (TXnCTL0) is set to 1, the count operation is started
in synchronization with the count clock.
When the value of the 16-bit timer counter Xn (TMXn) later matches the value of TXnCRm, TMXn is cleared to 0000H
and a match interrupt signal (INTTMXn) is generated. This INTTMXn signal enables TMXn to operate as an interval timer.
Remarks 1. For how to enable the INTTMXn interrupt, refer to CHAPTER 17 INTERRUPT FUNCTIONS.
2. m = 1, 3
n = 0, 1
Figure 6-18. Basic Timing Example of Interval Timer Operation
16-bit timer counter Xn
0000H
Operable bits
(TXnTMC)
Compare register
(TXnCRm)
Compare match interrupt
(INTTMXn)
N
10
N N N N
Interval
(N + 1)
Interval
(N + 1)
Interval
(N + 1)
Interval
(N + 1)
Remark m = 1, 3
n = 0, 1
<R>