Datasheet

78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1
R01UH0010EJ0500 Rev.5.00 205
Feb 28, 2012
Table 6-2. Register Setting Bits Controlling Operation Mode and 16-bit Timers X0 and X1 (2/2)
Operation mode
TMXn-only mode
(n = 0, 1)
Synchronous start mode
Synchronous start/clear
mode
Register Bit
TMX0 TMX1 Master
(TMX0)
Slave
(TMX1)
Master
(TMX0)
Slave
(TMX1)
TX0CMP1RP Setting Setting
 
TX0CMP1RM1,
TX0CMP1RM0
Setting is
valid
when
TX0CMP
1RP = 0

Setting is
valid
when
TX0CMP
1RP = 0
  
TX0CMP0RP Setting Setting
 
TX0CTL4
TX0CMP0RM1,
TX0CMP0RM0
Setting is
valid
when
TX0CMP
0RP = 0

Setting is
valid
when
TX0CMP
0RP = 0
  
TX1CMP1RM1,
TX1CMP1RM0

Setting is
valid
when
TX0CMP
1RP = 1

Setting is
valid
when
TX0CMP
1RP = 1
 
TX1CTL4
TX1CMP0RM1,
TX1CMP0RM0

Setting is
valid
when
TX0CMP
0RP = 1

Setting is
valid
when
TX0CMP
0RP = 1
 
TX0TOC1 Setting

Setting

Setting

TX0TOC0 Setting

Setting

Setting

TX0TOL1 Setting

Setting

Setting

TX0IOC0
TX0TOL0 Setting

Setting

Setting

TX1TOC1

Setting

Setting

Setting
TX1TOC0

Setting

Setting

Setting
TX1TOL1

Setting

Setting

Setting
TX1IOC0
TX1TOL0

Setting

Setting

Setting