Datasheet

78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1
R01UH0010EJ0500 Rev.5.00 204
Feb 28, 2012
The following table shows how the operation modes (TMX0-only mode, TMX1-only mode, TMX0 and TMX1
synchronous start mode, TMX0 and TMX1 synchronous start/clear mode) and register setting bits controlling 16-bit timers
X0 and X1 relate to each other.
Table 6-2. Register Setting Bits Controlling Operation Mode and 16-bit Timers X0 and X1 (1/2)
Operation mode
TMXn-only mode
(n = 0, 1)
Synchronous start mode
Synchronous start/clear
mode
Register Bit
TMX0 TMX1 Master
(TMX0)
Slave
(TMX1)
Master
(TMX0)
Slave
(TMX1)
TX0TMC Setting

Setting Setting TX0CTL0
TX0CKS2 to
TX0CKS0
Setting

Setting

Setting
TX1TMC

Setting
   
TX1CTL0
TX1CKS2 to
TX1CKS0

Setting

Setting
 
TX0INTPST Setting

0 Setting
TX0PWMCE Setting

Setting

Setting

TX0PWMCINV Setting

Setting Setting
TX0CTL1
TX0PWM Setting

Setting

Setting

TX1PWMCE

Setting

Setting

Setting
TX1PWM

Setting

Setting

Setting
TX1MD1

0

0

1
TX1CTL1
TX1MD0

0

1

0
TX0TRGS Setting

Setting

Setting

TX0ADEN Setting

Setting

Setting

TX0CTL2
TX0CCS Setting

Setting

Setting

TX1ADEN

Setting

Setting

Setting TX1CTL2
TX1CCS

Setting

Setting

Setting
TX0CMPLDSET1,
TX0CMPLDSET0
Setting

Setting

Setting
TX0INTP0RM1,
TX0INTP0RM0
Setting

Setting

Setting (setting
TX0INTP0RM1 = 1 and
TX0INTP0RM0 = 1 is
prohibited)
TX0CTL3
TX0CMP2RM1,
TX0CMP2RM0
Setting

Setting

Setting (setting
TX0CMP2RM1 = 1 and
TX0CMP2RM0 = 1 is
prohibited)