Datasheet

78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1
R01UH0010EJ0500 Rev.5.00 200
Feb 28, 2012
Figure 6-14. Format of 16-Bit Timer X1 Operation Control Register 4 (TX1CTL4)
Address: FF9AH After reset: 00H R/W
Symbol 7 6 5 <4> <3> 2 <1> <0>
TX1CTL4 0 0
0
TX1CMP1R
M1
TX1CMP1R
M0
0
TX1CMP0R
M1
TX1CMP0R
M0
TX1CMP1R
M1
TX1CMP1R
M0
Operation mode of interlocking function via comparator 1 output (interlocking with
TMX1 timer)
0 0 Disables operation of interlocking function via comparator 1 output.
0 1
Interlocking mode 1 (timer reset mode): Resets timer when comparator 1 output is at
high level (CMP1F flag = 1).
1 0
Interlocking mode 2 (timer restart mode): Restarts timer when rising edge of
comparator 1 output is detected.
1 1
Interlocking mode 3 (timer output reset mode): Resets timer output from detection of
rising edge of comparator 1 output to generation of next interrupt
Note
.
TX1CMP0R
M1
TX1CMP0R
M0
Operation mode of interlocking function via comparator 0 output (interlocking with
TMX1 timer)
0 0 Disables operation of interlocking function via comparator 0 output.
0 1
Interlocking mode 1 (timer reset mode): Resets timer when comparator 0 output is at
high level (CMP0F flag = 1).
1 0
Interlocking mode 2 (timer restart mode): Restarts timer when rising edge of
comparator 0 output is detected.
1 1
Interlocking mode 3 (timer output reset mode): Resets timer output from detection of
rising edge of comparator 0 output to generation of next interrupt
Note
.
Note Do not set to interlocking mode 3 when in TMX0 and TMX1 synchronous start/clear mode.
Caution During the timer operation, setting the other bits of TX1CTL4 is prohibited. However, TX1CTL4 can
be refreshed (the same value is written).