Datasheet
78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1
R01UH0010EJ0500 Rev.5.00 199
Feb 28, 2012
(5) 16-bit timer Xn operation control register 4 (TXnCTL4)
TXnCTL4 is a register that sets the mode of the interlocking function with comparator 0 and comparator 1.
TXnCTL4 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears TXnCTL4 to 00H.
Remark n = 0, 1
Figure 6-13. Format of 16-Bit Timer X0 Operation Control Register 4 (TX0CTL4)
Address: FF82H After reset: 00H R/W
Symbol 7 6 <5> <4> <3> <2> <1> <0>
TX0CTL4 0 0
TX0CMP1RP
TX0CMP1R
M1
TX0CMP1R
M0
TX0CMP0RP
TX0CMP0R
M1
TX0CMP0R
M0
TX0CMP1RP
Selection of timer interlocking with comparator 1 output
0 Comparator 1 output interlocks with TMX0 timer.
1 Comparator 1 output interlocks with TMX1 timer.
TX0CMP1R
M1
TX0CMP1R
M0
Operation mode of interlocking function via comparator 1 output (interlocking with
TMX0 timer)
0 0 Disables operation of interlocking function via comparator 1 output.
0 1
Interlocking mode 1 (timer reset mode): Resets timer when comparator 1 output is at
high level (CMP1F flag = 1).
1 0
Interlocking mode 2 (timer restart mode): Restarts timer when rising edge of
comparator 1 output is detected.
1 1
Interlocking mode 3 (timer output reset mode): Resets timer output from detection of
rising edge of comparator 1 output to generation of next interrupt
Note
.
TX0CMP0RP
Selection of timer interlocking with comparator 0 output
0 Comparator 0 output interlocks with TMX0 timer.
1 Comparator 0 output interlocks with TMX1 timer.
TX0CMP0R
M1
TX0CMP0R
M0
Operation mode of interlocking function via comparator 0 output (interlocking with
TMX0 timer)
0 0 Disables operation of interlocking function via comparator 0 output.
0 1
Interlocking mode 1 (timer reset mode): Resets timer when comparator 0 output is at
high level (CMP0F flag = 1).
1 0
Interlocking mode 2 (timer restart mode): Restarts timer when rising edge of
comparator 0 output is detected.
1 1
Interlocking mode 3 (timer output reset mode): Resets timer output from detection of
rising edge of comparator 0 output to generation of next interrupt
Note
.
Note Do not set to interlocking mode 3 when in TMX0 and TMX1 synchronous start/clear mode.
Caution During the timer operation, setting the other bits of TX0CTL4 is prohibited. However, TX0CTL4 can
be refreshed (the same value is written).