Datasheet

78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1
R01UH0010EJ0500 Rev.5.00 198
Feb 28, 2012
Figure 6-12. Format of 16-Bit Timer X0 Operation Control Register 3 (TX0CTL3)
Address: FF81H After reset: 00H R/W
Symbol 7 <6> <5> 4 <3> <2> <1> <0>
TX0CTL3 0
TX0CMPLD
SET1
TX0CMPLD
SET0
0
TX0INTP0R
M1
TX0INTP0R
M0
TX0CMP2R
M1
TX0CMP2R
M0
TX0CMPLD
SET1
TX0CMPLD
SET0
Change of compare register when restarting upon comparator output
(When interlocking mode 2 (timer restart mode) is set)
0 0 Does not change compare register value when restarting.
0 1
Rewrites values of all compare registers (TXnCR0 to TXnCR3, TXnCCR0)
Note 1
at
once when restarting upon comparator 0 output
Notes 2, 3
.
1 0
Rewrites values of all compare registers (TXnCR0 to TXnCR3, TXnCCR0)
Note 1
at
once when restarting upon comparator 1 output
Notes 2, 3
.
1 1
Rewrites values of all compare registers (TXnCR0 to TXnCR3, TXnCCR0)
Note 1
at
once when restarting upon comparator 2 output
Notes 2, 3
.
TX0INTP0R
M1
TX0INTP0R
M0
Operation mode of interlocking function via INTP0 (interlocking with TMX0 timer)
0 0 Disables operation of interlocking function via INTP0.
0 1 Interlocking mode 1 (timer reset mode): Resets timer when INTP0 is at high level.
1 0
Interlocking mode 2 (timer restart mode): Restarts timer when INTP0 rising edge is
detected.
1 1
Interlocking mode 3 (timer output reset mode): Resets timer output from detection of
INTP0 rising edge to generation of next interrupt
Note 4
.
TX0CMP2R
M1
TX0CMP2R
M0
Operation mode of interlocking function via comparator 2 output (interlocking with
TMX0 timer)
0 0 Disables operation of interlocking function via comparator 2 output.
0 1
Interlocking mode 1 (timer reset mode): Resets timer when comparator 2 output is at
high level (CMP2F flag = 1).
1 0
Interlocking mode 2 (timer restart mode): Restarts timer when rising edge of
comparator 2 output is detected.
1 1
Interlocking mode 3 (timer output reset mode): Resets timer output from detection of
rising edge of comparator 2 output to generation of next interrupt
Note 4
.
Notes 1. The values of TX1CR0 to TX1CR3 and TX1CCR0 are rewritten at once only in the TMX0 and TMX1
synchronous start/clear mode.
2. For TMX0 single output, the values of the compare registers are rewritten at once upon restart by
comparator output after TX0CR1 is rewritten.
3. For TMX0 dual output, the values of the compare registers are rewritten at once upon restart by
comparator output after TX0CR3 is rewritten.
4. Do not set to interlocking mode 3 when in TMX0 and TMX1 synchronous start/clear mode.
Caution During the timer operation, setting the other bits of TX0CTL3 is prohibited. However, TX0CTL3 can
be refreshed (the same value is written).