Datasheet

78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1
R01UH0010EJ0500 Rev.5.00 197
Feb 28, 2012
Figure 6-11. Format of 16-Bit Timer X1 Operation Control Register 2 (TX1CTL2)
Address: FF96H After reset: 00H R/W
Symbol 7 6 5 4 3 2 <1> <0>
TX1CTL2 0 0 0 0 0 0 TX1ADEN TX1CCS
TX1ADEN Control of generating A/D conversion synchronization trigger from TMX1
0 Disables generating A/D conversion synchronization trigger
1
Enables generating A/D conversion synchronization trigger
Note
TX1CCS TX1CCR0 register operation
0
Operates as compare register
Note
1 Operates as capture register
Note When enabling generation of the A/D conversion synchronization trigger (TX1ADEN = 1), set the TX1CCR0
register to operate as a compare register (TX1CCS = 0), because the A/D conversion synchronization trigger is
generated upon a match between the counter and the TX1CCR0 register.
Cautions 1. During the 16-bit timer operation, setting the other bits of TX1CTL2 is prohibited. However,
TX1CTL2 can be refreshed (the same value is written).
2. The registers used by the A/D converter (ADM0, ADPC0, ADPC1, ADS) can be rewritten while the
16-bit timer X1 is operating.
3. A/D conversion synchronization triggers that occur while A/D conversion is stopped (ADCS = 0)
are invalid. A/D conversion synchronization triggers that occur after A/D conversion has been
enabled (ADCS = 1) are valid.
(4) 16-bit timer X0 operation control register 3 (TX0CTL3)
TX0CTL3 is a register that sets the mode of the interlocking function with comparator 2 and INTP0, and sets the
operation when restarting upon comparator output.
TX0CTL3 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears TX0CTL3 to 00H.