Datasheet

78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1
R01UH0010EJ0500 Rev.5.00 196
Feb 28, 2012
Remarks 1. The capture trigger sources are as follows, according to the operation mode.
Operation mode Capture trigger sources
TMX0-only start mode INTCMP2, INTP0
TMX1-only start mode INTCMP1
TMX0 INTCMP2, INTP0
TMX0 and TMX1 Synchronous start
mode
TMX1 INTCMP1
TMX0 INTCMP2, INTP0
TMX0 and TMX1 Synchronous
start/clear mode
TMX1 INTCMP1
2. n = 0, 1
Figure 6-10. Format of 16-Bit Timer X0 Operation Control Register 2 (TX0CTL2)
Address: FF80H After reset: 00H R/W
Symbol 7 <6> 5 4 3 2 <1> <0>
TX0CTL2 0 TX0TRGS 0 0 0 0 TX0ADEN TX0CCS
TX0TRGS TMX0 capture trigger source selection
0 INTCMP2
1 INTP0
TX0ADEN Control of generating A/D conversion synchronization trigger from TMX0
0 Disables generating A/D conversion synchronization trigger
1
Enables generating A/D conversion synchronization trigger
Note
TX0CCS TX0CCR0 register control
0
Operates as compare register
Note
1 Operates as capture register
Note When enabling generation of the A/D conversion synchronization trigger (TX0ADEN = 1), set the TX0CCR0
register to operate as a compare register (TX0CCS = 0), because the A/D conversion synchronization trigger is
generated upon a match between the counter and the TX0CCR0 register.
Cautions 1. During the 16-bit timer X0 operation, setting the other bits of TX0CTL2 is prohibited. However,
TX0CTL2 can be refreshed (the same value is written).
2. The registers used by the A/D converter (ADM0, ADPC0, ADPC1, ADS) can be rewritten while the
16-bit timer X0 is operating.
3. A/D conversion synchronization triggers that occur while A/D conversion is stopped (ADCS = 0)
are invalid. A/D conversion synchronization triggers that occur after A/D conversion has been
enabled (ADCS = 1) are valid.