Datasheet
78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1
R01UH0010EJ0500 Rev.5.00 195
Feb 28, 2012
Cautions 2. Be sure to clear bits 0 to 2, 6 to 0.
3. When using the output gate function, set bit 0 (TOEN1) of the TMHMD1 register to 1 (enable the
TOH1 output).
Figure 6-9. Format of 16-Bit Timer X1 Operation Control Register 1 (TX1CTL1)
Address: FF95H After reset: 00H R/W
Symbol 7 6 <5> 4 <3> 2 <1> <0>
TX1CTL1 0 0 TX1PWM
CE
0 TX1PWM 0 TX1MD1 TX1MD0
TX1PWM
CE
Control of TOX1n output gate function by TOH1 output (n = 0, 1)
0 Does not use output gate function.
1 Use output gate function.
TX1PWM TMX1 PWM output operation setting
0
Single output (TOX10 pin only)
INTTMX1 is generated upon match of counter and TX1CR1 register
1
Dual output (TOX10 and TOX11 pins)
INTTMX1 is generated upon match of counter and TX1CR3 register
TX1MD1 TX1MD0 Operation mode setting
0 0 TMX1-only start mode
0 1 TMX0 and TMX1 Synchronous start mode
1 0 TMX0 and TMX1 Synchronous start/clear mode
1 1 Setting prohibited
Cautions 1. During the timer operation, setting the other bits of TX1CTL1 is prohibited. However, TX1CTL1
can be refreshed (the same value is written).
2. Be sure to clear bits 2, 4, 6 and 7 to 0.
3. When using the output gate function, set bit 0 (TOEN1) of the TMHMD1 register to 1 (enable the
TOH1 output).
(3) 16-bit timer Xn operation control register 2 (TXnCTL2)
TXnCTL2 is a register that selects the capture trigger source, controls the generation of the A/D conversion
synchronization trigger, and sets the TXnCCR0 register.
TXnCTL2 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears TXnCTL2 to 00H.